Top 10k strings from clock.lst in <root> / src / z80 / Clock.zip /
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4 call PrintChar 3 jr nz, Print 3 call N2DEC 3 add hl, hl 2 ld a, (SecCount) 2 ld a, (MinCount) 2 ld a, (HourCount) 2 ld (SecCount), a 2 ld (MinCount), a 2 ld (HourCount), a 2 call DigitLoop 1 savebin "clock.bin", Start, EndIntRoutine - Start 1 org INT_VEC*256 + INT_VEC - (EndLdr - Start) 1 org INT_VEC*256 + INT_VEC 1 ld ix, SCR_OFF + 6 1 ld ix, SCR_OFF + 5 1 ld ix, SCR_OFF + 3 1 ld ix, SCR_OFF + 2 1 ld ix, SCR_OFF 1 ld de, INT_VEC*256 + INT_VEC 1 ld de, (FNT_TBL_ADDR) 1 ld bc, StartIntRoutine - OverHead 1 ld bc, EndIntRoutine - IntRoutine 1 ld bc, -10 1 ld a, INT_VEC - 1 1 ld a, (hl) 1 ld a, (TickCount) 1 ld (ix), a 1 ld (TickCount), a 1 ld de, 256 1 ld bc, -256*8 + 1 1 jr nz, Clean 1 jp ROM_INT_HANDLER 1 hl, (INT_VEC-1) << 8 1 equ 16384 + 32 - 8 1 djnz PrintLine 1 djnz FillIntTbl 1 cp TICS_PER_SEC 1 c, DivNrLoop 1 add ix, de 1 add ix, bc 1 add hl, de 1 add hl, bc 1 a, INT_VEC 1 a, '0' - 1 1 DEVICE ZXSPECTRUM48 1 ;this will re-enable interupts 1 ;substract divizor 1 ;still dividing? 1 ;set interrupt 1 ;screen offset address for display 1 ;number of tics per second 1 ;nope, restore 1 ;move int routine to proper address (INT_VEC*256) + INT_VEC 1 ;interrupt vector value 1 ;increase reminder 1 ;from 2 consecutive values from interval (INT_VEC-1)*256 to (INT_VEC-1)*256 + 255. 1 ;font table pointer system variable 1 ;find font address 1 ;create vector table 1 ;257 values are required, cos the interrupt handler address is read 1 197 FEC5 1 196 FEC5 1 195 FEC5 EndIntRoutine: 1 194 FEC4 00 HourCount 1 193 FEC3 00 MinCount 1 192 FEC2 00 SecCount 1 191 FEC1 00 TickCount 1 190 FEC1 1 189 FEC0 C9 1 188 FEBE ED 42 1 187 FEBC 38 FC 1 186 FEBB 09 1 185 FEBA 3C 1 184 FEBA DivNrLoop: 1 183 FEB8 3E 2F 1 182 FEB8 DigitLoop: 1 181 FEB8 1 180 FEB8 1 179 FEB7 C9 1 178 FEB4 CD 7A FE 1 177 FEB2 DD 09 1 176 FEAF 01 01 F8 1 175 FEAE 7A 1 174 FEAD D1 1 173 FEAA CD 7A FE 1 172 FEA9 D5 1 171 FEA8 7B 1 170 FEA8 PrintNo: 1 169 FEA8 1 168 FEA7 57 1 167 FEA4 CD B8 FE 1 166 FEA1 01 FF FF 1 165 FEA0 5F 1 164 FE9D CD B8 FE 1 163 FE9A 01 F6 FF 1 162 FE98 26 00 1 161 FE97 6F 1 160 FE97 N2DEC: 1 159 FE97 ;OUT: DE = 2 digit representation of A 1 158 FE97 ;IN : A = number 1 157 FE97 1 156 FE97 1 155 FE96 C9 1 154 FE96 1 153 FE94 10 F7 1 152 FE93 23 1 151 FE91 DD 19 1 150 FE8E DD 77 00 1 149 FE8D 7E 1 148 FE8D PrintLine: 1 147 FE8D 1 146 FE8B 06 08 1 145 FE88 11 00 01 1 144 FE87 19 1 143 FE86 29 1 142 FE85 29 1 141 FE84 29 1 140 FE83 6F 1 139 FE81 26 00 1 138 FE7F D6 20 1 137 FE7E 14 1 136 FE7A ED 5B 36 5C 1 135 FE7A 1 134 FE7A PrintChar: 1 133 FE7A ;IN: IX = address, A = char 1 132 FE7A 1 131 FE79 C9 1 130 FE76 CD 97 FE 1 129 FE72 DD 21 1E 40 1 128 FE6F 3A C2 FE 1 127 FE6C CD 7A FE 1 126 FE68 DD 21 1D 40 1 125 FE66 3E 3A 1 124 FE63 CD 97 FE 1 123 FE5F DD 21 1B 40 1 122 FE5C 3A C3 FE 1 121 FE59 CD 7A FE 1 120 FE55 DD 21 1A 40 1 119 FE53 3E 3A 1 118 FE50 CD 97 FE 1 117 FE4C DD 21 18 40 1 116 FE49 3A C4 FE 1 115 FE49 Print: 1 114 FE49 1 113 FE46 32 C4 FE 1 112 FE45 AF 1 111 FE43 20 04 1 110 FE41 FE 18 1 109 FE3E 32 C4 FE 1 108 FE3D 3C 1 107 FE3A 3A C4 FE 1 106 FE3A 1 105 FE37 32 C3 FE 1 104 FE36 AF 1 103 FE34 20 13 1 102 FE32 FE 3C 1 101 FE2F 32 C3 FE 1 100 FE2E 3C 1 099 FE2B 3A C3 FE 1 098 FE2B 1 097 FE28 32 C2 FE 1 096 FE27 AF 1 095 FE25 20 22 1 094 FE23 FE 3C 1 093 FE20 32 C2 FE 1 092 FE1F 3C 1 091 FE1C 3A C2 FE 1 090 FE1C Payload: 1 089 FE1C 1 088 FE19 C3 38 00 1 087 FE18 F1 1 086 FE17 E1 1 085 FE16 C1 1 084 FE15 D1 1 083 FE13 DD E1 1 082 FE10 32 C1 FE 1 081 FE10 Clean: 1 080 FE0F AF 1 079 FE0F 1 078 FE0C CD 1C FE 1 077 FE0C 1 076 FE0A 20 04 1 075 FE08 FE 32 1 074 FE07 3C 1 073 FE04 3A C1 FE 1 072 FE04 1 071 FE02 DD E5 1 070 FE01 D5 1 069 FE00 C5 1 068 FDFF E5 1 067 FDFE F5 1 066 FDFD F3 1 065 FDFD 1 064 FDFD IntRoutine: 1 063 FDFD 1 062 FDFD 1 061 FDFD StartIntRoutine: 1 060 FDFD 1 059 FDFD ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 058 FDFD ;The interrupt handler part 1 057 FDFD 1 056 FDFD 1 055 FDFD 1 054 FDFD EndLdr: 1 053 FDFC C9 1 052 FDFC Return: 1 051 FDFC 1 050 FDFB FB 1 049 FDF9 ED 5E 1 048 FDF7 ED 47 1 047 FDF5 3E FC 1 046 FDF4 F3 1 045 FDF4 1 044 FDF4 1 043 FDF2 ED B0 1 042 FDEF 01 C8 00 1 041 FDEC 11 FD FD 1 040 FDEC 1 039 FDEB 09 1 038 FDE8 01 18 00 1 037 FDE7 E1 1 036 FDE6 3B 1 035 FDE5 3B 1 034 FDE5 OverHead: 1 033 FDE2 CD 52 00 1 032 FDE2 1 031 FDE2 1 030 FDE1 77 1 029 FDDF 10 FC 1 028 FDDE 23 1 027 FDDD 77 1 026 FDDD FillIntTbl: 1 025 FDDB 06 00 1 024 FDD9 3E FD 1 023 FDD6 21 00 FC 1 022 FDD6 1 021 FDD6 1 020 FDD6 1 019 FDD6 Start: 1 018 FDD6 1 017 0000 1 016 0000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 015 0000 ;The setup part 1 014 0000 1 013 0000 1 012 0000 TICS_PER_SEC 1 011 0000 ROM_INT_HANDLER 1 010 0000 FNT_TBL_ADDR 1 009 0000 1 008 0000 SCR_OFF 1 007 0000 INT_VEC 1 006 0000 ;vector table is at 252 * 256 = 64512 to 64769 1 005 0000 ;253 * 256 = 64768 => interrupt handler is at 64768 + 253 = 65021. 1 004 0000 1 003 0000 1 002 0000 1 001 0000 ;Interrupt based clock, v1, (C) George Chirtoaca, August 2007.