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2 (bug fixed on 20040225). 1 the initial setup. Same format as for .in files. 1 the format: 1 tests.expected 1 says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236. 1 port low bit set or reset). 1 of 'events': each has the format 1 now specifies the final time. 1 d{3,b}_{1,2,3}: check for correct port contention on IO in the four 1 dd00.in, ddfd00.in: test timings of "extended NOP" opcodes DD 00 and 1 cb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to 1 Why some specific tests are here 1 Then followed by lines specifying the initial memory setup. Each has 1 I R IFF1 IFF2 IM <halted> <tstates> 1 Finally, -1 to end the test. Blank lines may follow before the next test. 1 File formats 1 Each test output starts with the test description, followed by a list 1 Each test has the format: 1 After that, lines specifying which bits of memory have changed since 1 After that, lines specifying AF, BC etc as for .in files. <tstates> 1 AF BC DE HL AF' BC' DE' HL' IX IY SP PC 1 ================================ 1 ============ 1 <type> is one of MR (memory read), MW (memory write), MC (memory 1 <tstates> specifies the number of tstates to run the test for, in 1 <time> is simply the time at which the event occurs. 1 <time> <type> <address> <data> 1 <start address> <byte1> <byte2> ... -1 1 <halted> specifies whether the Z80 is halted. 1 <data> is the byte written or read. Missing for contentions. 1 <arbitrary test description> 1 <address> is the address (or IO port) affected. 1 37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5 1 1234 56 78 9a -1 1 -------------- 1 instruction is allowed to complete. 1 decimal; the number actually executed may be higher, as the final 1 tests are now essentially redundant. 1 on 20060722). 1 next opcode executes at the right time (bug fixed 1 and 5 are copied on all BIT instructions, so these 1 However, later research has revealed the bits 3 1 F only for BIT 3,<arg> and BIT 5,<arg> respectively 1 DD FD 00; the extra 00 at the end is to check the 1 contend), PR (port read), PW (port write) or PC (port contend). 1 relevant states (port high byte in 0x40 to 0x7f or not,